By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in response to Moore’s legislations? At this second, there is not any effortless resolution for the reason that gate scaling is swiftly rising as a major roadblock for the evolution of CMOS know-how. Channel engineering according to high-mobility semiconductor fabrics (e.g. strained Si, substitute orientation substrates, Ge or III-V compounds) might support conquer the hindrances in view that they give functionality enhancement. There are a number of matters notwithstanding. can we know the way to make complicated engineered substrates (e.g. Germanium-on-Insulator)? that are the simplest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? will we procedure those fabrics in brief channel transistors utilizing flows, toolsets and understand how just like that during Si know-how? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed to this point, what's the state of the art and that are the most demanding situations forward prior to we come any on the subject of a conceivable Ge and III-V MOS technology.
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